Software program engineer Ben C. has constructed a instrument that bridges the worlds of {hardware} description languages (HDLs) with development and administration sim Factorio — bringing chip designs, as much as and together with a working RISC-V processor, into the sport.
“Shortly after Factorio 2.0 launched I noticed that you can in all probability describe combinator circuits as Verilog and have a compiler translate it,” Ben C. explains of the venture’s inspiration. “Thats what this venture is. Enter Verilog, output pure vanilla Factorio Blueprints. I took this new launch as a chance to dive into a brand new venture and a brand new language! At first I used to be simply attempting to study rust and compilers, however it developed into an enormous software program experiment. I added Lua scripting, a nodes-based GUI (net and native help with egui), a combinator simulator, graph partitioning, SVG era, ILP solvers, hyper parameter optimization. Actually its a bag of many issues I used to be occupied with.”
For those who’ve ever wished you can take a Verilog design and switch it right into a Factorio manufacturing facility, right now is your fortunate day. (📷: Ben C.)
Verilog is a {hardware} description language (HDL), a sort of domain-specific language (DSL) tailor-made to the design of chips — both to be executed in simulation on a pc, become gateware to be used with a field-programmable gate array (FPGA) or different programmable logic system, or taped out for manufacturing into an precise bodily application-specific built-in circuit (ASIC). Factorio, in the meantime, launched in 2020 as a development and administration simulation from Wube Software program — and obtained a serious improve, often called Factorio 2.0, in 2024.
“To perform this I make use of two packages,” Ben. C explains. “The primary is a front-end compiler to take Verilog and produce a graph of logic which could be roughly translated into Factorio logic. On the finish of this course of we’re left with a combination of fine-grained logic and coarse grain word-level representations. Now Rust enters the image. I now learn this JSON into what I name a ‘MappedDIt’sgn;’ there are some further tweaks to make the format of a MappedDesign extra favorable, however it’s not that essential. Its primarily a deserialized Yosys output.””
“To perform this I make use of two packages,” Ben. C explains. “The primary is a front-end compiler to take Verilog and produce a graph of logic which could be roughly translated into Factorio logic. On the finish of this course of we’re left with a combination of fine-grained logic and coarse grain word-level representations. Now Rust enters the image. I now learn this JSON into what I name a ‘MappedDesign;’ there are some further tweaks to make the format of a MappedDesign extra favorable, however its not that essential. Its primarily a deserialized Yosys output.”
The toolchain permits for even advanced designs to be transformed and imported into the sport, together with a 32-bit RISC-V CPU. (📷: Ben C.)
The compilation then turns to bodily planning, utilizing in-game combinators and wiring constructions to construct the design piece-by-piece. “As a result of the routing will place energy poles,” Ben C. explains, “we will reuse them for energy distribution. Very first thing is to find out if every combinator is roofed by an influence distribution space, if some combinators are lacking, I place a brand new pole to maximise protection over lacking areas. Then as soon as I’m glad with protection I do a heuristic primarily based graph traversal to attempt to reduce [the] variety of copper wires whereas additionally ensuring we solely have one energy distribution community. Typically this is not good, however works properly sufficient. I believe for the RISC-V core I solely wanted to manually place a pair substations to get full protection.”
Extra particulars on the venture can be found in Ben C.’s Reddit put up, whereas supply code is accessible on GitHub beneath the GNU Affero Normal Public License 3; a dwell web site internet hosting the back-end circulate “with a GUI slapped on prime,” for simulation and experimentation, is accessible on the developer’s web site.