Jane Road has launched a contest for FPGA builders, utilizing the puzzles set throughout this 12 months’s Creation of Code to advertise options based mostly on synthesizable {hardware} — and entrants can win prizes as much as and together with an AMD Zynq UltraScale+ Kria KV260 FPGA improvement equipment for his or her entries.
“Creation of Code has lengthy been a favourite December ritual at Jane Road, with many collaborating within the month-long puzzle problem that encourages considerate engineering and out-of-the-box considering — very a lot our sort of enjoyable,” Jane Road’s Benjamin Devlin explains. “Final 12 months, Anish, a {hardware} engineer at Jane Road, wrote about tackling the complete sequence in Hardcaml, our OCaml-based {hardware} DSL, turning these puzzles into synthesizable FPGA circuits. In case you missed it, his submit, Creation of Hardcaml, walks you thru how implementing such algorithms in {hardware} grew to become a novel train in architectural design and useful resource optimization.”
Fancy an FPGA-flavored problem? Strive jane Road’s Creation of FPGA and you possibly can win an AMD Zynq dev board. (📷: AMD)
Now, the corporate is trying to encourage others to do the identical with the 2025 Creation of FPGA problem. The concept: taking the programming puzzles set annually by Eric Wastl, who based the Creation of Code problem sequence again in 2015, and fixing them in {hardware} moderately than software program.
“When the ultimate AoC 2025 puzzle drops, choose any puzzles you want (not less than one and as much as as many as you need) to construct synthesizable RTL with life like I/O [Input/Output],” Devlin and Anish Singhani clarify. “Bonus factors if you happen to do it in Hardcaml. We’re excited to see the intelligent designs created throughout the tutorial and open‑supply communities, and we’d additionally like to get extra individuals attempting Hardcaml!”
Extra info on the competitors, entries for which shut on January 16, 2026, is on the market on the Jane Road weblog.